The present invention relates generally to an integrated circuit (IC) design, and more particularly to a laterally diffused metal-oxide-semiconductor (LDMOS) device with improved electrostatic discharge (ESD) performance.
As semiconductor devices continue to shrink in size, their susceptibility to ESD damage becomes an increasingly important reliability concern. An ESD event occurs when electrostatic charge is transferred between one or more pins of an IC and another object in a short period of time. The rapid charge transfer often generates voltages large enough to break down insulating films of semiconductor devices, thereby causing permanent damages. In order to protect the semiconductor devices from ESD damages, various protection circuits can be implemented at the input and output pins of the IC to shunt ESD currents away from sensitive internal structures.
The LDMOS transistor is one kind of the semiconductor devices that are particularly susceptible to damages caused by the ESD event. The LDMOS device, featured by its extended source or drain doped region, is often found in circuits operating in high voltages, such as 5, 12, 40, 100 and 1000 volts. Conventionally, the LDMOS transistor requires some additional devices or circuit modules to protect it from ESD damages. These ESD protection devices and circuit modules typically require a separate set of fabrication process steps different from those for the LDMOS transistors. Thus, the addition of these ESD protection devices and circuit modules increases the costs of manufacturing ICs that have LDMOS transistors implemented thereon.
As such, it is desirable to have a LDMOS transistor with improved ESD protection performance, thereby eliminating the need for other additional ESD protection devices and circuit modules.